The field of this invention relates to a radio frequency amplifier module, an integrated circuit device, a wireless communication unit and a method therefor. The invention is applicable to, but not limited to, a method and apparatus for digitally controllable amplification of an RF signal.
The near-far effect is a situation that is common in wireless communication systems. The near-far effect is a condition in which a strong (e.g. near) signal captures a receiver making it difficult for the receiver to detect a weaker (e.g. far off) signal. The near-far effect is particularly problematic in code division multiple access (CDMA) systems where transmitters share transmission frequencies and transmission time.
To overcome the near-far effect, wireless communications systems such as the 3rd Generation (3G) of mobile telephone standards and technology (WCDMA, TDSCDMA, etc) developed by the 3rd Generation Partnership Project (3GPP™) (www.3gpp.org), require a wide range (e.g. around 74 dB) of accurate power control within the transmitters. Radio frequency amplifier gain control range is the range, usually given in dB, between the smallest and largest gain levels. To cover process and temperature variations, a gain control range of at least, say, 85 dB is desirable. Digitally programmable driver amplifiers are most widely used in deep-submicron CMOS 3G transmitter architectures.
The lowest gain settings are often limited by signal leakage. As such, in conventional transmitters, most of the gain control range is typically implemented at the radio frequency for better carrier leakage performance at low power levels. Additionally, finite isolation of the off-state gain cells can limit the gain control range that can be practically implemented in a single stage. Accordingly, in conventional transmitter implementations, more than one gain control stage is typically adopted to achieve enough isolation at low power levels to achieve a wide gain control range. However, additional stages increase both current and area. Also more stages make it more difficulties to meet the stringent noise and linearity requirements for a 3G SAW-less transmitter design.
FIG. 1 illustrates a simplified circuit diagram of an example of a digitally programmable amplifier 100. The paper “Direct-Conversion WCDMA Transmitter with −163 dBc/Hz Noise at 190 MHz Offset”; Analog Devices, West Mailing, United Kingdom, which is published in Solid-State Circuits Conference, 2007, ISSCC 2007, Digest of Technical Papers, IEEE International, describes an example of such a digital programmable amplifier, and is incorporated in its entirety herein by reference.
The amplifier 100 comprises a first, less significant bits (LSB) component 110 comprising a resistor attenuator ladder 115, which in the illustrated example comprises an R-2R resistor attenuator ladder, and a plurality of gain cells 120 coupled to respective ‘tap’ points within the R-2R resistor attenuator ladder 115. Each gain cell 120 within the LSB component 110 is arranged to receive, and be controllable via, a respective less significant control bit (b0, b1, b2, b3) 125. In some examples, the gain cells 120 within the LSB component 110 comprise equal gain cells. The R-2R resistor attenuator ladder 115 is operably coupled to a load impedance (Zload) 105 of the amplifier 100. In this manner, the LSB component 110 of the amplifier 100 is arranged to drive an LSB output current component of the amplifier 100 in accordance with the less significant control bits 125. In some examples, only one gain cell 120 within the LSB component 110 is switched on (via the respective control bit 125) at a time.
The amplifier 100 further comprises a further, more significant bit(s) (MSB) component 130 coupled to the load impedance 105 of the amplifier, either directly or via a balun or the like (not shown), bypassing the R-2R resistor attenuator ladder 115 of the LSB component 110. The MSB component 130 comprises one or more gain cells 140 operably coupled in parallel and each arranged to receive, and be controllable via, respective more significant control bits (b4, b5, b6, b7) 145. In some examples, the gain cells 140 of the MSB component 130 may comprise unary weighted cells, binary weighted cells, or a combination of unary and binary weighted cells. In some examples, each gain cell 140 within the MSB component 130 may be switched ‘on’ and ‘off’ (via the respective control bit 145) substantially independently of the other gain cells 140 within the MSB component 130.
In some examples, the LSB component 110 and the MSB component 130 are arranged to operate exclusively of each other such that when a gain cell 120 of the LSB component 110 is switched on, all gain cells 140 of the MSB component 130 are switched off. Conversely, when at least one gain cell 140 of the MSB component 130 is switched on, all gain cells 120 of the LSB component 110 are switched off.
The number of R-2R stages within the R-2R resistor attenuator ladder 115 typically depends on the gain control requirement. In the illustrated example, a four-stage R-2R resistor attenuator ladder 115 is illustrated, for example enabling a 24 dB gain control range.
Referring now to FIG. 2, there is illustrated a simplified circuit diagram of an example of an implementation of a unit gain cell, such as one of the unit gain cells 120, 140 within the LSB component 110 and/or the MSB component 130 of the amplifier 100. In the example illustrated in FIG. 2, one of the unit gain cells 140 of the MSB component 130 is illustrated and comprises a cascode common source amplifier 200. An RF input voltage (Vin) 245 to be amplified is provided to a gate 212 of a first transistor (M1) 210 within the cascode common source amplifier 200. The RF input voltage 245 comprises an alternating current (AC) signal and a direct current (DC) bias voltage. The control bit signal (Vb) 145 is provided to a gate 222 of a second transistor (M2) 220 within the cascode common source amplifier 200. In this manner, the control bit signal 145 provides a static enable control voltage to bias the gate 222 of the second transistor (M2) 220 to ‘turn on’ or ‘turn off’ the cascode common source amplifier 200. Notably, such a cascode common source amplifier 200 may also be used to implement the gain cells 120 of the LSB component 110 of the amplifier 100.
Referring now to FIG. 3, there is illustrated a simplified circuit diagram of the digitally programmable amplifier 100 of FIG. 1 in which the gain cells 120, 140 of the LSB and MSB components 110, 130 are implemented by way of cascode common source amplifiers, such as the cascode common source amplifier 200 illustrated in FIG. 2. For simplicity, only a single gain cell 120, 140 within each of the LSB and MSB components 110, 130 is illustrated in FIG. 3. The RF input voltage (Vin) 245 to be amplified, comprising an AC RF signal (V1) 310 and a DC bias voltage (Vin_bias) 315, is provided to the gate of a first transistor (M1) 320, (M5) 340 within the cascode common source amplifier of each of the gain cells 120, 140 of the LSB and MSB components 110, 130. The control bit signals 125, 145 (FIG. 1) are provided to the gate of a second transistor (M1c) 325, (M5c) 345 within the cascode common source amplifier of each of the gain cells 120, 140 of the LSB and MSB components 110, 130.
In the scenario illustrated in FIG. 3, the digitally programmable amplifier 100 is programmed to operate in a minimum power level mode, whereby a least significant control bit signal 125 (Vb) is ‘set’ in order to turn on the least significant gain cell 120 within the LSB component 130 (i.e. the left-most gain cell in the illustrated example). All other control bit signals 125, 145 are ‘unset’ in order to turn off all other gain cells 120, 140 within the digitally programmable amplifier 100. Accordingly, a gate of the second transistor (M5c) 345 within the cascode common source amplifier of the gain cell 140 of the MSB component 130 is illustrated as being tied to ground. As such, in this minimum power level mode, the digitally programmable amplifier 100 is operating at a lowest end of its gain control range.
A ‘wanted’ signal 350 is output to the load impedance 105 by the R-2R resistor attenuator ladder 115 as a result of the least significant gain cell 120 within the LSB component 110 being turned on. An unwanted leaked signal 355 is also illustrated in FIG. 3. This unwanted leaked signal 355 is a result of a signal leakage path 360 through the gain cells 140 within the MSB component 130.
FIG. 4 illustrates a simplified circuit diagram of a small signal equivalent network for the gain cells 140 of the MSB component 130 when in an off-state, such as illustrated in FIG. 3. Even when in such an off-state, the RF input voltage 245 to be amplified is received at the gate 410 of the first transistor (M5) 340 within the cascode common source amplifier of each gain cell 140 within the MSB component 130. The small signal equivalent network illustrated in FIG. 4 is representative of all of the gain cells 140 within the MSB component 130. Accordingly, the combined gate-to-drain capacitance (Cgd_M5) 415 of the first transistors (M5) 340 within the gain cells 140 within the MSB component 130 is sufficient to couple the RF input voltage 245 to the drain node 420 thereof, which also comprises the respective source node of the second transistor (M5c) 345 within the gain cell 140. Thus, the source node 420 of the second transistor (M5c) 345 will see a voltage swing resulting from the RF input voltage 245, which will leak through the second transistor (M5c) 345 network, which comprises parasitic capacitances 430 from gate to drain/source overlap, body to drain/source junctions and metal routing etc, to the load impedance 105 in the form of the unwanted leak signal 355.
When the digitally programmable amplifier 100 is programmed to operate in a minimum power level mode, as illustrated in FIG. 3, this unwanted leak signal 355 is particular significant compared to the low level wanted output signal 350, and thus has a significant impact on the achievable gain control range.
FIG. 5 illustrates a simplified circuit diagram of the digitally programmable amplifier 100 of FIG. 3 comprising a known solution to improving the isolation of the gain cells 140 within the MSB component 130 when in an off state. A shunt switch (M5—s) 510 is coupled between the mutual node 420 (of FIG. 4) of the cascode common source amplifier of the gain cell 140 and ground. In this manner, the shunt switch M5—s 510 may be closed (e.g. by setting EN to high in the illustrated example) in order to tie the mutual node 420 of the cascode common source amplifier of the gain cell 140 to ground. In this manner, the voltage across drain output resistance (Rout_M5) 440 (FIG. 4) of the cascode common source amplifier is reduced, thereby reducing the swing seen by the source node 420 (of FIG. 4) of the second transistor (M5c) 345 of the cascode common source amplifier, and thus the leakage signal there through. Thus, improved isolation of the gain cells 140 is achieved without the need for additional gain control stages. However, such a solution results in additional parasitic capacitance on the drain of the first transistor (M5) 340 of the cascode common source amplifier, which is not desirable during high gain operation; i.e. when the gain cell 140 is in an on state. In addition, the inclusion of such a shunt switch (M5—s) 510 to all gain cells 140 within the MSB component 130 increases layout complexity and die area.
Thus, a need exists for an improved RF amplifier module, and method of operation thereof.